Data interface and high-speed communication system using the same

ABSTRACT

A data interface for communicating data between processors having: a writing-side register group in which data in a writing-side processor which transmits data is written in response to a clock signal; a reading-side register group into which the data written into the writing-side register group is transferred and written in response to a later clock operation, the data being read out by a reading-side processor of a data receiving side; a write controller for selectively writing data in a register in the writing-side register group in accordance with an address signal and a write signal of the writing-side processor; and a read controller for selectively reading data from a register in the reading-side register group in accordance with an address signal of the reading-side processor; so that a double buffer structure consisting of the writing-side buffers and the reading-side buffers causes the address signal and the data signal to individually be connected in the writing side and the reading side. Thus, the respective processors are able to transfer data without mutual interference.

TECHNICAL FIELD

The present invention relates to a data interface for communicating databetween processors and a high-speed-communication system using theinterface.

BACKGROUND ART

The present invention relates to an interface which is capable of, athigh speed, communicating (transmitting and receiving) data betweenmicroprocessors when, for example, a mechanical structure, e.g., anelectric motor, which must be controlled, is controlled by a processingsystem having a multiprocessor structure with a plurality ofmicroprocessors, and to a high-speed-communication system using theinterface.

Hitherto, when control is performed by a plurality of microprocessors, amethod using serial transmission or parallel transmission ortransmission using a dual port memory has been employed, in whichcommands, messages and various control information items arecommunicated between a microprocessor (hereinafter called a“control-side processor”) for receiving from an object to be controlledinformation indicating the state of the object, performing a calculationfrom the received control information, and directly issuing a command tothe object to be controlled and a microprocessor (hereinafter called a“central processor”) for issuing a command to a sole processor or aplurality of control-side processors in accordance with informationobtained from a transmission interface, man-machine interface or anexternal interface. The transmission using the dual port memory isperformed in such a manner that read/write from the control side, thecentral side or both sides to and from the dual port memory is performedin accordance with a transfer procedure previously determined betweenthe control side and the central side to communicate commands, messagesand various control information items.

When various control information items are communicated among onecentral processor and a plurality of control-side processors, thefollowing conditions must be satisfied:

(1) Although the timing at which information is transmitted from thecentral processor to each of the control-side processor is relativelylong compared to the short time high-speed operation cycle of thehigh-speed sampling performed in each of the control-side processors,data communication must be reliably performed during the transmissiontiming;

(2) Since the data which must be communicated between the centralprocessor and each of the control-side processors can have tens tohundreds of word units, the circuit function must be larger than thevolume of data which can be transmitted in one transmission operation;

(3) Considering the short-time high-speed operation cycle of high-speedsampling performed by each of the control-side processors, the centralprocessor is inhibited from performing a process which affects theoperation time of each of the control-side processors and which islonger than the operation period (cycle) for each of the control-sideprocessors. Also, when the central processor transmits information toand receives information from each of the control-side processors, thecentral processor must not perform a process which affects itsprocessing time and which is longer than its operation cycle;

(4) Since control information data which is communicated between thecentral processor and the control-side processor in a single operationis in the form of a block having conformability or unity, an occurrencein which a success in communication of certain data items and a failurein communication of certain data items in the same block must beinhibited.

To satisfy the above-mentioned conditions, a method of realizing aoperation architecture and a circuit between the single centralprocessor and a plurality of control-side processors has been asfollows.

In conventional serial transmission, synchronous or asynchronoustransfer can be selected. If one word has a volume of one byte andinformation about one word is communicated, two processors attempting tocommunicate are able to conduct the communication without mutualinterference. However, if the quantity of data, which must becommunicated, is larger than the above-mentioned quantity, the receiverside must inform the transmission-side processor of receipt of data topermit the transmission-side processor to transfer next data. As aresult, two processors having different operation cycles must perform ahandshake operation to send the confirmation information “completion oftransmission/incompletion of transmission” and “completion ofreceipt/incompletion of receipt” between the central processor and thecontrol-side processor which have communicated with each other. Toperform the process for confirming communication completion of controlinformation data, both transmission and receipt-side processorsundesirably interfere in the other's operation processing periods witheach other. Thus, the processing time is excessively elongated.

It might be considered feasible to arrange the conventional serialtransmission in such a manner that a large buffer for storing data in aquantity of tens to hundreds of words is provided as a received-datastorage buffer of an interface circuit block so that a receiptcompletion flag is set when a predetermined number of data has beenreceived to enable the receiving-side processor to determine whetherstart of the data receiving operation is permitted. Even so, since thetiming at which the control-side processor or the central processorreads data from the buffer of the serial interface and the timing atwhich the serial interface supplies data to the buffer coincide witheach other, there is the great possibility that the processor with alonger operation period fails to receive data. Thus, data cannot bereliably received with predetermined sampling and the reliability inreceiving data deteriorates.

To prevent this, a dedicated high-speed-communication processor must beprovided for each of the two communication terminals to exclusivelyperform error processing and the like. In this case, a communicationprocessor is employed, resulting in that a problem arises which is thesame as that experienced with the communication between the centralprocessor and the control-side processor to determine a procedure fortransferring data of control information between the communicationprocessor and the central processor or the control-side processorwithout affecting the mutual operation processes of the processors.

The parallel transmission must be performed in such a manner thatcontrol information data is communicated at a transfer timingsynchronous between the two sides. If either side performs anotherprocess during the process for communicating control information dataattributable to interruption or the like, data transfer cannot beperformed. In this case, either of the two sides always performs theinterruption process for another and thus the mutual operationprocessing periods (cycles) are allowed to interfere with each other,thus causing the processing time to be excessively elongated.

In a transmission using a dual port memory, access can be inhibited by aBUSY terminal or the like to inhibit access for either side when theother side is making an access. Thus, the two sides are able toindividually perform operations without the necessity of establishingsynchronization. However, a central processor having a long operationprocessing period fails to write control information data on the dualport memory (that is, transmit data) when each of the control-sideprocessors with short operation processing periods are reading data inthe dual port memory in advance. Although data can again be transmittedafter the failure, in the communication of the control information withkeeping a conformability or unity of the sequential data items which aretransmitted in one transmission operation, it is not possible to providethe control-side processor with the time inhibiting reading of the dualport memory, by means of the circuit structure of only the dual portmemory. Moreover, the operation for again transmitting data from thecentral processor results in the operation processing time for thecentral processor being excessively elongated.

In Japanese Utility Model Unexamined Publication No. 1-91959, anarrangement has been disclosed in which two buffers for writing andreading are provided to transfer data between the two buffers after apredetermined time has elapsed from receipt of a writing signal or areading signal. However, if the operation speeds of the operatingapparatuses for performing the communication are different from eachother or if the data communication frequencies are different from eachother, reliable data transmission between the buffers cannot beperformed sometimes.

SUMMARY OF THE INVENTION

To solve the above-mentioned problems, an object of the presentinvention is to provide a data interface for communicating (transmittingand receiving) control information data between processors in such amanner that interference with the mutual calculation processingoperation/time is prevented, as well as to provide a high-speedcommunication system using the data interface.

Another object of the present invention is to obtain a data interfacewhich enables data transmission to be performed in such a manner thatcontrol information data, which is communicated between processors inone operation, is formed into a block and conformability or unity(compatibility) of data items is maintained, and ahigh-speed-communication system using the foregoing data interface.

In view of the foregoing, according to the present invention, there isprovided a data interface for communicating data between processors,comprising: a writing-side register group on which data in awriting-side processor of a data transmitting side is written inresponse to a clock signal; a reading-side register group into which thedata written into the writing-side register group is transferred andwritten in response to a later clock operation, the data being read outby a reading-side processor of a data receiving side; write controlmeans for selectively writing data on a register in the writing-sideregister group in accordance with an address signal and a write signalof the writing-side processor; and read control means for selectivelyreading data from a register in the reading-side register group inaccordance with an address signal of the reading-side processor.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans includes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data on theregister in the writing-side register group in accordance with theaddress signal and the write signal of the writing-side processor, and awriting-side selector circuit provided for each register in thewriting-side register group and arranged to normally select dataobtained by feeding back data in the corresponding register in thereading-side register group and to select data in the writing-sideprocessor to supply data to the register in the writing-side registergroup when selected in response to the writing select signal, and theread control means includes; a register reading select-signal generatingcircuit for generating a reading select signal for selectively readingthe register in the reading-side register group in accordance with theaddress signal of the reading-side processor, and a reading-sideselector circuit connected to each register in the reading-side registergroup and arranged to output, to the reading-side processor, data in theregister in the reading-side register group selected in accordance withthe reading select signal.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans inhibits data transfer from the writing-side register group to thereading-side register group during a period in which the reading-sideprocessor is reading data and causes data to automatically betransferred after reading has been completed.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans includes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data on theregister in the writing-side register group in accordance with theaddress signal and the write signal of the writing-side processor, awriting-side selector circuit provided for each register in thewriting-side register group and arranged to normally select dataobtained by feeding back data in the register in the writing-sideregister group and to select data in the writing-side processor tosupply data to the register in the writing-side register group whenselected in response to the writing select signal, and a secondwriting-side selector circuit provided for each register in thereading-side register group and arranged to normally select data in thecorresponding register in the writing-side register group and to selectdata obtained by feeding back data in the register in the reading-sideregister group to supply data to the register in the reading-sideregister group when the read signal of the reading-side processor is ina read state, and the read control means includes; a register readingselect-signal generating circuit for generating a reading select signalfor selectively reading the register in the reading-side register groupin accordance with the address of the reading-side processor, and areading-side selector circuit connected to each register in thereading-side register group and arranged to output, to the reading-sideprocessor, data in the register in the reading-side register groupselected in accordance with the reading select signal.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans inhibits data transfer from the writing-side register group to thereading-side register group during a period in which the writing-sideprocessor performs writing and causes data to be collectivelytransferred to the reading-side register group when writing on aspecific address has been performed.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans includes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data on theregister in the writing-side register group in accordance with theaddress signal and the write signal of the writing-side processor, awriting-side selector circuit provided for each register in thewriting-side register group and arranged to normally select dataobtained by feeding back data in the register in the writing-sideregister group and to select data in the writing-side processor tosupply data to the register in the writing-side register group whenselected in response to the writing select signal, awrite-completion-signal generating circuit for generating a writecompletion signal for causing data to be collectively transferred fromthe writing-side register group to the reading-side register whenwriting on a predetermined address has been performed in accordance withthe address signal and the write signal of the writing-side processor,and a second writing-side selector circuit provided for each register inthe reading-side register group and arranged to normally select dataobtained by feeding back data in the register in the reading-sideregister group and to select data in the corresponding register in thewriting-side register group to supply data to the register in thereading-side register group when the write completion signal indicatescompletion of writing, and the read control means includes: a registerreading select-signal generating circuit for generating a reading selectsignal for selectively reading the register in the reading-side registergroup in accordance with the address signal of the reading-sideprocessor, and a reading-side selector circuit connected to eachregister in the reading-side register group and arranged to output, tothe reading-side processor, data in the register in the reading-sideregister group selected in accordance with the reading select signal.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans inhibits data transfer from the writing-side register to thereading-side register during a period in which the writing-sideprocessor is reading a predetermined address space and causes data toautomatically be transferred to the reading-side register group whenreading of a predetermined address space has been completed.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans includes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data on theregister in the writing-side register group in accordance with theaddress signal and the write signal of the writing-side processor, awriting-side selector circuit provided for each register in thewriting-side register group and arranged to normally select dataobtained by feeding back data in the register in the writing-sideregister group and to select data in the writing-side processor tosupply data to the register in the writing-side register group whenselected in response to the writing select signal, aread-completion-signal generating circuit for generating a readcompletion signal for causing data to be collectively transferred fromthe writing-side register group to the reading-side register group whena predetermined address has been read in accordance with the addresssignal and the read signal of the reading-side processor, and a secondwriting-side selector circuit provided for each register in thereading-side register group and arranged to normally select dataobtained by feeding back data in the register in the reading-sideregister group and to select data in the corresponding register in thewriting-side register group to supply data to the register in thereading-side register group when the read completion signal indicatescompletion of reading, and the read control means includes: a registerreading select-signal generating circuit for generating a reading selectsignal for selectively reading the register in the reading-side registergroup in accordance with the address signal of the reading-sideprocessor, and a reading-side selector circuit connected to eachregister in the reading-side register group and arranged to output, tothe reading-side processor, data in the register in the reading-sideregister group selected in accordance with the reading select signal.

According to the another aspect of the present invention, there isprovided a data interface having a structure where the write controlmeans inhibits data transfer from the writing-side register to thereading-side register during a period in which the writing-sideprocessor is writing data and a period in which the reading-sideprocessor is reading a predetermined address space and causes data toautomatically be transferred to the reading-side register group whenwriting on a specific address has been performed or when reading of apredetermined address space has been completed.

According to the another aspect of the present invention, there isprovided a data interface hating a structure where the write controlmeans includes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data on theregister in the writing-side register group in accordance with theaddress signal and the write signal of the writing-side processor, awriting-side selector circuit provided for each register in thewriting-side register group and arranged to normally select dataobtained by feeding back data in the register in the writing-sideregister group and to select data in the writing-side processor tosupply data to the register in the writing-side register group whenselected in response to the writing select signal, awrite/read-completion-signal generating circuit for generating a writecompletion signal and a read completion signal for collectivelytransferring data from the writing-side register group to thereading-side register when writing on a predetermined address has beenperformed and when reading of a predetermined address has been performedin accordance with the address signal and the write signal of thewriting-side processor and the address signal and the read signal of thereading-side processor, and a second writing-side selector circuitprovided for each register in the reading-side register group andarranged to normally select data obtained by feeding back data in theregister in the reading-side register group and to select data in thecorresponding register in the writing-side register group to supply datato the register in the reading-side register group when the writecompletion signal and the read completion signal indicates completion ofwriting and reading, and the read control means includes: a registerreading select-signal generating circuit for generating a reading selectsignal for selectively reading the register in the reading-side registergroup in accordance with the address signal of the reading-sideprocessor, and a reading-side selector circuit connected to eachregister in the reading-side register group and arranged to output, tothe reading-side processor, data in the register in the reading-sideregister group selected in accordance with the reading select signal.

According to the another aspect of the present invention, there isprovided a high-speed communication system comprising a first processor,a dedicated high-speed-communication processor connected to the firstprocessor, a second processor connected to the first processor throughthe dedicated high-speed-communication processor to transfer data to andfrom the first processor and data interfaces respectively providedbetween the first processor and the dedicated high-speed-communicationprocessor and between the dedicated high-speed-communication processorand the second processor, wherein the data interface includes: awriting-side register group on which data of the processor of a datatransmission side is written in response to a clock signal; areading-side register group into which the data written into thewriting-side register group is transferred and written in response to alater clock operation, the data being read out by a reading-sideprocessor of a data receiving side; write control means for selectivelywriting data on a register in the writing-side register group inaccordance with an address signal and a write signal of the processor ofa data transmission side; and read control means for selectively readingdata from a register in the reading-side register group in accordancewith an address signal of the processor of a data receiving side.

BRIEF DESCRIPTION DRAWINGS

FIG. 1 is a block diagram showing the structure of an interfaceaccording to an embodiment of the present invention;

FIG. 2 is a block diagram showing the structure of an interfaceaccording to another embodiment of the present invention;

FIG. 3 is a block diagram showing the structure of an interfaceaccording to another embodiment of the present invention;

FIG. 4 is a block diagram showing the structure of an interfaceaccording to another embodiment of the present invention;

FIG. 5 is a block diagram showing the structure of an interfaceaccording to another embodiment of the present invention;

FIG. 6 is a block diagram showing the structure of ahigh-speed-communication system according to another embodiment of thepresent invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of a data interface according to the present invention and ahigh-speed communication system using the data interface will now bedescribed. In the drawings showing the embodiments, identical or similarelements are given the same reference numerals.

First Embodiment

FIG. 1 is a diagram showing the structure of a data interface accordingto an embodiment of the present invention.

The data interface according to this embodiment is provided between acontrol-side processor for directly issuing a command to, for example,an elevator group which is an object which must be controlled in asystem for administrating an elevator group and a central processor forissuing a command to one or a plurality of the control-side processorsin accordance with information input from a call button on each floor ora destination instruction button in an elevator car. A writing-sideprocessor is a processor for transmitting data, while a reading-sideprocessor is a processor for receiving data. In the above-mentionedsystem for administrating an elevator group, data to be transmitted iscontrol information data.

Referring to FIG. 1, reference numerals 10 a to 10 e representinput-signal terminals. The terminals 10 a to 10 c respectively aresupplied with address signals, write signals and data signals from thewriting-side processor. The terminal 10 d is supplied with a registerwriting clock signal, while the terminal 10 e is supplied with anaddress signal of the reading-side processor. Reference numeral 11represents an output-signal terminal from which a data signal is outputto the reading-side processor.

Reference numeral 12 represents a writing-side register group composedof register circuits 12-1 to 12-n in which data is written from thewriting-side processor, 13 represents a reading-side register groupcomposed of register circuits 13-1 to 13-n from which data is read fromthe reading-side processor.

Reference numerals 14-1 to 14-n represent writing-side selector circuitsprovided for respective register circuits and arranged to select eitherdata signals supplied from the writing-side processors or data fed backfrom the corresponding register circuits 13-1 to 13-n to supply selecteddata to the writing-side register circuits 12-1 to 12-n respectively.

Reference numeral 15 represents a register writing select-signalgenerating circuit which generates a register writing select-signal forwriting to a corresponding register circuit among the register circuits12-1 to 12-n in response to an address signal 10 a and a write signal 10b of the writing-side processor.

The register circuits 12-1 to 12-n and 13-1 to 13-n and the selectorcircuits 14-1 to 14-n are provided in parallel in the same numbercorresponding to the number (n) of words which must be written as thedata items.

Reference numeral 16 represents a register reading select-signalgenerating circuit which generates a register reading select-signal forselecting the data signal, which must be output to the reading-sideprocessor, from corresponding register circuit among the registercircuits 13-1 to 13-n in response to an address signal 10 e of thereading-side processor. Reference numeral 17 represents a reading-sideselector circuit which follows the reading select signal to output thedata signal of the selected reading-side register circuit to a data busof the reading-side processor.

Note that the writing-side selector circuits 14-1 to 14-n and theregister writing select-signal generating circuit 15 form a writecontrol means, while the register reading select-signal generatingcircuit 16 and the reading-side selector circuit 17 form a read controlmeans.

The operation will now be described. A normal operation is performed asfollows: when the address signal and the write signal output from thewriting-side processor have been brought to a significant state, theregister writing select-signal generating circuit 15 generates theselect signals to control the selector circuits 14-1 to 14-n so as tocause the data signal 10 c in the data bus of the writing-side processorto sequentially be written on the writing-side register circuits 12-1 to12-n. If the selector circuit 14-1 has been selected in response to theselect signal, the data signal 10 c of the writing-side processor iswritten on the register circuit 12-1 through the selector circuit 14-1in response to a clock signal 10 d. In the next clock operation, thecontents of the writing-side register circuit 12-1 are transferred andwritten on the corresponding reading-side register circuit 13-1connected to the register circuit 12-1.

When the writing operation has been completed and the writing-side writesignal 10 b has been brought to a non-significant state (a state inwhich no writing operation is indicated), the register writingselect-signal generating circuit 15 generates select signals for feedingback the data signals stored in the corresponding register circuits 13-1to 13-n corresponding to the writing-side selector circuits 14-1 to 14-nrespectively to the writing-side register circuits 12-1 to 12-n tomaintain the contents of the register circuits.

When an address signal 10 e of the reading-side processor has beensupplied to the register reading select-signal generating circuit 16, aregister reading select signal is generated to the reading-side selectorcircuit 17. The selector circuit 17 follows the select signal to outputthe value of the corresponding reading-side register circuit 13 to thereading-side processor as the data signal.

Since a double buffer structure is formed in which the writing-sideregister circuits 12-1 to 12-n and the reading-side registers 13-1 to13-n are individually provided, the address signal and the data signalare individually connected to the writing-side and the reading-side.Thus, data transfer can be performed without interference between theprocessors.

Second Embodiment

FIG. 2 is a diagram showing the structure of a data interface accordingto another embodiment of the present invention. In this embodiment, thewriting operation and the reading operation are made to be independentfrom each other to improve reliability by employing a structure in whichthe value of the writing-side register group 12 is not automaticallytransferred to the reading-side register circuit 13 when thereading-side processor is performing a reading operation even after thewriting-side processor has immediately completed the writing operation.The value of the writing-side register group 12 is automaticallytransferred to the reading-side register 13 after the reading operationhas been completed.

Referring to FIG. 2, second writing-side selector circuits 18-1 to 18-nrespectively provided for the registers 13-1 to 13-n of the reading-sideregister group 13 follow the read signal of the reading-side processorsupplied from an input signal terminal 10 f to select either data fromthe corresponding and connected register circuit in the writing-sideregister circuit group 12 or data obtained by feeding back data in thereading-side register group 13 to supply the selected data item to thereading-side register circuits 13-1 to 13-n.

Note that the writing-side selector circuits 14-1 to 14-n, the registerwriting select-signal generating circuit 15 and the second reading-sideselector circuits 18-1 to 18-n form the write control means, while theregister reading select-signal generating circuit 16 and thereading-side selector circuit 17 form the read control means.

The state of the selector circuit 18 is normally selected such that dataof the corresponding register circuit 12, to which the reading side isconnected, is written on the selector circuit 18 as a result of a clocksynchronizing operation immediately after the writing-side register 12has been written. When the reading-side processor starts the readingoperation and the read signal 10 f is brought to a significant state(indicating a read operation state), the selector circuit 18 feeds backthe data value in the reading-side register circuit 13 to maintain thepresent value. When the read signal 10 f is brought to a non-significantstate (indicating no reading operation), the selector circuit 18 isreturned to a normal state so that a state is realized in which datafrom the writing-side register circuit 12 is selected. In response tothe next clock synchronizing signal, the value of the writing-sideregister circuit 12 is automatically transferred to the reading-sideregister circuit 13.

As a result, data transfer can be performed in such a manner that thereading operation of the reading-side processor is not affected by thewriting operation of the writing-side processor.

Third Embodiment

FIG. 3 is a diagram showing the structure of the data interfaceaccording to another embodiment of the present invention. In thisembodiment, data is collectively transferred from the writing-sideregister circuit 12 to the reading-side register circuit 13 when all thewriting operations from the writing-side processor have been completed.

Referring to FIG. 3, a write-completion-signal generating circuit 19 isprovided which generates a select signal to be supplied to each of thesecond writing-side selector circuits 18-1 to 18-n for determining inputto the register circuits 13-1 to 13-n.

The writing-side selector circuits 14-1 to 14-n, the register writingselect-signal generating circuit 15, the second writing-side selectorcircuits 18-1 to 18-n and the write-completion-signal generating circuit19 form the write control means, while the register readingselect-signal generating circuit 16 and the reading-side selectorcircuit 17 form the read control means.

Although the second embodiment has the structure in which the selectsignal is generated in response to the read signal of the reading-sideprocessor, this embodiment has a structure that the address signal 10 aand the write signal 10 b of the writing-side processor are used as thedata transfer condition to the reading-side register circuit 13. Thewrite-completion-signal generating circuit 19 generates write completionsignal for permitting data transfer from the writing-side registercircuit 12 to each of the corresponding reading-side register circuit 13in a writing operation on a specific address of the writing-sideprocessor. That is, after the writing-side processor has completedwriting on all of the writing-side register circuits 12, writing to acertain address is performed so that collective data transfer from allof the writing-side register circuits 12-1 to 12-n to the reading-sideregister circuits 13-1 to 13-n is enabled.

As shown in FIG. 3, the read signal 10 f of the reading-side processoraccording to the second embodiment may be added to the condition underwhich the completion signal is generated by the write-completion-signalgenerating circuit 19. In this case, a state where the reading-sideprocessor is not performing a reading operation is employed as anadditional condition for generating the write completion signal.

Fourth Embodiment

FIG. 4 is a diagram showing the structure of a data interface accordingto another embodiment of the present invention. In this embodiment, whendata is required to be read to the reading-side processor in such amanner that a sequential data items having conformability or unity areread, automatic transfer of data from the writing-side register circuit12 to the reading-side register circuit 13 is not performed inconsideration of time lapse and the like during a period (cycle) inwhich the reading-side processor is reading a certain address space.

In the structure shown in FIG. 4, a read-completion-signal generatingcircuit 20 is provided which generates a select signal to the secondwriting-side selector circuits 18-1 to 18-n which determines input tothe reading-side register circuits 13-1 to 13-n respectively. Theaddress signal 10 e and the read signal 10 f of the reading-sideprocessor are used as the conditions under which data can be transferredto the reading-side register circuit 13.

Note that the writing-side selector circuits 14-1 to 14-n, the registerwriting select-signal generating circuit 15, the second writing-sideselector circuits 18-1 to 18-n and the read-completion-signal generatingcircuit 20 form the write control means, while the register readingselect-signal generating circuit 16 and the reading-side selectorcircuit 17 form the read control means.

As a result, data is not transferred from the writing-side registercircuit 12 to the reading-side register circuit 13 until thereading-side processor completes reading of a certain space. Thus,sequential data items read in a certain address area are unified interms of time and the data items above can be viewed as reliable dataitems having conformability.

Fifth Embodiment

FIG. 5 is a diagram showing the structure of the data interfaceaccording to another embodiment of the present invention. Thisembodiment has a structure formed by combining the functions of thesecond, third and fourth embodiments so that data transfer iscollectively performed from the writing-side register circuit 12 to thereading-side register circuit 13 when writing from the writing-sideprocessor has been completed. Moreover, in a period in which thereading-side processor is reading a certain address area, automatictransfer of data from the writing-side register circuit 12 to thereading-side register circuit 13 is inhibited.

Referring to FIG. 5, a write/read-completion-signal generating circuit21 is provided which generates a select signal for each of the secondwriting-side selector circuits 18-1 to 18-n for determining input to thereading-side register circuits 13-1 to 13-n. The address signal 10 a andthe write signal 10 b of the writing-side processor and the addresssignal 10 e and the read signal 10 f of the reading-side processor areemployed as conditions under which data is transferred to thereading-side register circuit 13.

Note that the writing-side selector circuits 14-1 to 14-n, the registerwriting select-signal generating circuit 15, the second writing-sideselector circuits 18-1 to 18-n and the write/read-completion-signalgenerating circuit 21 form the write control means, while the registerreading select-signal generating circuit 16 and the reading-sideselector circuit 17 form the read control means.

As a result, after the writing-side processor has written data on all ofthe register circuits 12, it writes data on a specific address so thatcollective data transfer from all of the writing-side register circuits12-1 to 12-n to the reading-side register circuits 13-1 to 13-n isenabled. Moreover, data is not transferred from the writing-sideregister circuit 12 to the reading-side register circuit 13 until thereading-side processor completes reading of a certain space. Thus,sequential data items read in a certain address area are unified interms of time and the data items above are reliable data items havingconformability.

Sixth Embodiment

FIG. 6 is a diagram showing the structure of a high-speed-communicationsystem according to another embodiment of the present invention.Referring to FIG. 6, reference numeral 40 represents a centralprocessor, which is a first processor, 41 represents a control-sideprocessor which is a second processor, 42 represents an dedicatedhigh-speed-communication processor for establishing the connectionbetween the central processor 40 and the control-side processor 41, and43 a and 43 b represent the data interfaces according to the foregoingembodiments and respectively connected between the central processor 40and the dedicated high-speed-communication processor 42 and between thededicated high-speed-communication processor 42 and the centralprocessor 41.

When data transfer is performed between the central processor 40 and thededicated high-speed-communication processor 42 and between thededicated high-speed-communication processor 42 and the control-sideprocessor 41, the processor which transmits data acts as a writing-sideprocessor. On the other hand, the processor which receives data acts asthe reading-side processor. Thus, the data interfaces 43 a and 43 battain the effects described in the foregoing embodiments.

INDUSTRIAL APPLICABILITY

As described above, according to the present invention, the datainterface for communicating data between processors, comprises awriting-side register group on which data in a writing-side processor ofa data transmitting side is written in response to a clock signal; areading-side register group into which the data written into thewriting-side register group is transferred and written in response to alater clock operation, the data being read out by a reading-sideprocessor of a data receiving side; write control means for selectivelywriting data on a register in the writing-side register group inaccordance with an address signal and a write signal of the writing-sideprocessor; and read control means for selectively reading data from aregister in the reading-side register group in accordance with anaddress signal of the reading-side processor. Thus, the double bufferstructure including of the writing side registers and the reading sideregisters is formed. Therefore, the address signal and the data signalare individually connected in the writing side and the reading side. Asa result, the respective processors are able to transfer data withoutmutual interference.

Further the present invention is arranged in such a manner that thewrite control means inhibits data transfer from the writing-sideregister group to the reading-side register group during a period inwhich the reading-side processor is reading data and causes data toautomatically be transferred after reading has been completed.Therefore, the reading operation, which is conducted by the reading-sideprocessor, can be performed without influence from the writing operationwhich is performed by the writing-side processor. As a result,reliability in the data transfer can be improved.

Further the present invention is arranged in such a manner that thewrite control means inhibits data transfer from the writing-sideregister group to the reading-side register group during a period inwhich the writing-side processor performs writing and causes data to becollectively transferred to the reading-side register group when writingon a specific address has been performed. Therefore, when writing of aseries of the registers from the writing-side processor has beencompleted, data can collectively be transferred to the reading-sideregister.

Further more, the present invention is arranged in such a manner thatthe write control means inhibits data transfer from the writing-sideregister to the reading-side register during a period in which thewriting-side processor is reading a predetermined address space andcauses data to automatically be transferred to the reading-side registergroup when reading of a predetermined address space has been completed.Therefore, data is not transferred from the writing-side register to thereading-side register during a period in which the reading-sideprocessor is reading a certain address area. Therefore, the address areain the reading-side processor can always be read as sequential dataitems having conformability or unity.

Further more, the present invention is arranged in such a manner thatthe write control means inhibits data transfer from the writing-sideregister to the reading-side register during a period in which thewriting-side processor is writing data and a period in which thereading-side processor is reading a predetermined address space andcauses data to automatically be transferred to the reading-side registergroup when writing on a specific address has been performed or whenreading of a predetermined address space has been completed. Therefore,when writing on sequential registers from the writing-side processor hasbeen completed, data can collectively be transferred to the reading-sideregisters. Moreover, data is not transferred from the writing-sideregister to the reading-side register during a period in which thereading-side processor is reading a certain address space. Therefore,the address area in the reading-side processor can always be read assequential data items having conformability or unity.

Further more, the high speed communication system according to thepresent invention comprises the first processor, a dedicatedhigh-speed-communication processor connected to the first processor, asecond processor connected to the first processor through the dedicatedhigh-speed-communication processor to transfer data to and from thefirst processor, and data interfaces respectively provided between thefirst processor and the dedicated high-speed-communication processor andbetween the dedicated high-speed-communication processor and the secondprocessor, wherein the data interface includes a writing-side registergroup on which data of the processor of a data transmission side iswritten in response to a clock signal, a reading-side register groupinto which the data written into the writing-side register group istransferred and written in response to a later clock operation, the databeing read out by a reading-side processor of a data receiving side,write control means for selectively writing data on a register in thewriting-side register group in accordance with an address signal and awrite signal of the processor in a data-transmitting-side, and readcontrol means for selectively reading data from a register in thereading-side register group in accordance with an address signal of theprocessor in a data-receiving-side. Therefore, even if the dedicatedhigh-speed-communication processor is provided between the writing-sideprocessor and the reading-side processor, high-speed data transfer,which is free from mutual interference and which does not affect therespective calculating processes, can be performed between thewriting-side processor and the dedicated high-speed-communicationprocessor and between the dedicated high-speed-communication processorand the reading-side processor.

What is claimed is:
 1. A data interface for communicating data betweenprocessors, comprising: a writing-side register group in which data in awriting-side processor of a data transmitting side is written inresponse to a clock signal; a reading-side register group into which thedata written into said writing-side register group is transferred andwritten in response to a later clock operation, the data being read outby a reading-side processor of a data receiving side; write controlmeans for selectively writing data in a register in said writing-sideregister group in accordance with an address signal and a write signalof said writing-side processor; and read control means for selectivelyreading data from a register in said reading-side register group inaccordance with an address signal of said reading-side processor.
 2. Thedata interface according to claim 1, wherein said write control meansincludes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data in theregister in said writing-side register group in accordance with theaddress signal and the write signal of said writing-side processor, anda writing-side selector circuit for each register in said writing-sideregister group and arranged to select data obtained by feeding back datain the corresponding register in said reading-side register group and toselect data in said writing-side processor to supply data to theregister in said writing-side register group when selected in responseto the writing select signal, and said read control means includes: aregister reading select-signal generating circuit for generating areading select signal for selectively reading the register in saidreading-side register group in accordance with the address signal ofsaid reading-side processor, and a reading-side selector circuitconnected to each register in said reading-side register group andarranged to output, to said reading-side processor, data in the registerin said reading-side register group selected in accordance with thereading select signal.
 3. The data interface according to claim 1,wherein said write control means inhibits data transfer from saidwriting-side register group to said reading-side register group during aperiod in which said reading-side processor is reading data and causesdata to automatically be transferred after reading has been completed.4. The data interface according to claim 3, wherein: said write controlmeans includes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data on theregister in said writing-side register group in accordance with theaddress signal and the write signal of said writing-side processor, awriting-side selector circuit for each register in said writing-sideregister group and arranged to select data obtained by feeding back datain the register in said writing-side register group and to select datain said writing-side processor to supply data to the register in saidwriting-side register group when selected in response to the writingselect signal, and a second writing-side selector circuit for eachregister in said reading-side register group and arranged to select datain the corresponding register in said writing-side register group and toselect data obtained by feeding back data in the register in saidreading-side register group to supply data to the register in saidreading-side register group when the read signal of said reading-sideprocessor is in a read state, and said read control means includes:register reading select-signal generating circuit for generating areading select signal for selectively reading the register in saidreading-side register group in accordance with the address of saidreading-side processor, and a reading-side selector circuit connected toeach register in said reading-side register group and arranged tooutput, to said reading-side processor,- data in the register in saidreading-side register group selected in accordance with the readingselect signal.
 5. The data interface according to claim 1, wherein saidwrite control means inhibits data transfer from said writing-sideregister group to said reading-side register group during a period inwhich said writing-side processor writes data and causes data to becollectively transferred to said reading-side register group whenwriting at a specific address has been performed.
 6. The data interfaceaccording to claim 5, wherein: said write control means includes: aregister writing select-signal generating circuit for generating awriting select signal for selectively writing data on the register insaid writing-side register group in accordance with the address signaland the write signal of said writing-side processor, a writing-sideselector circuit for each register in said writing-side register groupand arranged to select data obtained by feeding back data in theregister in said writing-side register group and to select data in saidwriting-side processor to supply data to the register in saidwriting-side register group when selected in response to the writingselect signal, a write-completion-signal generating circuit forgenerating a write completion signal for causing data to be collectivelytransferred from said writing-side register group to said reading-sideregister when writing in a specific address has been performed inaccordance with the address signal and the write signal of saidwriting-side processor, and a second writing-side selector circuit foreach register in said reading-side register group and arranged to selectdata obtained by feeding back data in the register in said reading-sideregister group and to select data in the corresponding register in saidwriting-side register group to supply data to the register in saidreading-side register group when said write completion signal indicatescompletion of writing, and said read control means includes: a registerreading select-signal generating circuit for generating a reading selectsignal for selectively reading the register in said reading-sideregister group in accordance with the address signal of saidreading-side processor, and a reading-side selector circuit connected toeach register in said reading-side register group and arranged tooutput, to said reading-side processor, data in the register in saidreading-side register group selected in accordance with the readingselect signal.
 7. The data interface according to claim 1, wherein saidwrite control means inhibits data transfer from said writing-sideregister to said reading-side register during a period in which saidwriting-side processor is reading a specific address space and causesdata to automatically be transferred to said reading-side register groupwhen reading of the specific address space has been completed.
 8. Thedata interface according to claim 7, wherein: said write control meansincludes: a register writing select-signal generating circuit forgenerating a writing select signal for selectively writing data in theregister in said writing-side register group in accordance with theaddress signal and the write signal of said writing-side processor, awriting-side selector circuit for each register in said writing-sideregister group and arranged to select data obtained by feeding back datain the register in said writing-side register group and to select datain said writing-side processor to supply data to the register in saidwriting-side register group when selected in response to the writingselect signal, a read-completion-signal generating circuit forgenerating a read completion signal for causing data to be collectivelytransferred from said writing-side register group to said reading-sideregister group when a predetermined address has been read in accordancewith the address signal and the read signal of said reading-sideprocessor, and a second writing-side selector circuit for each registerin said reading-side register group and arranged to select data obtainedby feeding back data in the register in said reading-side register groupand to select data in the corresponding register in said writing-sideregister group to supply data to the register in said reading-sideregister group when said read completion signal indicates completion ofreading, and said read control means includes: a register readingselect-signal generating circuit for generating a, reading select signalfor selectively reading the register in said reading-side register groupin accordance with the address signal of said reading-side processor,and a reading-side selector circuit connected to each register in saidreading-side register group and arranged to output, to said reading-sideprocessor, data in the register in said reading-side register groupselected in accordance with the reading select signal.
 9. The datainterface according to claim 1, wherein said write control meansinhibits data transfer from said writing-side register to saidreading-side register during a period in which said writing-sideprocessor is writing data and a period in which said reading-sideprocessor is reading a specified address space and causes data toautomatically be transferred to said reading-side register group whenwriting in a specific address has been performed or when reading of thespecific address space has been completed.
 10. The data interfaceaccording to claim 9, wherein: said write control means includes: aregister writing select-signal generating circuit for generating awriting select signal for selectively writing data in the register insaid writing-side register group in accordance with the address signaland the write signal of said writing-side processor, a writing-sideselector circuit for each register in said writing-side register groupand arranged to select data obtained by feeding back data in theregister in said writing-side register group and to select data in saidwriting-side processor to supply data to the register in saidwriting-side register group when selected in response to the writingselect signal, a write/read-completion-signal generating circuit forgenerating a write completion signal and a read completion signal forcollectively transferring data from said writing-side register group tosaid reading-side register when writing in a specific address has beenperformed and when reading of the specific address has been performed inaccordance with the address signal and the write signal of saidwriting-side processor and the address signal and the read signal ofsaid reading-side processor, and a second writing-side selector circuitfor each register in said reading-side register group and arranged toselect data obtained by feeding back data in the register in saidreading-side register group and to select data in the correspondingregister in said writing-side register group to supply data to theregister in said reading-side register group when said write completionsignal and said read completion signal indicates completion of writingand reading, and said read control means includes: a register readingselect-signal generating circuit for generating a reading select signalfor selectively reading the register in said reading-side register groupin accordance with the address signal of said reading-side processor,and a reading-side selector circuit connected to each register in saidreading-side register group and arranged to output, to said reading-sideprocessor, data in the register in said reading-side register groupselected in accordance with the reading select signal.
 11. A high-speedcommunication system comprising a first processor, a dedicatedhigh-speed-communication processor, connected to said first processor, asecond processor connected to said first processor through saiddedicated high-speed-communication processor to transfer data to andfrom said first processor, and data interfaces respectively providedbetween said first processor and said dedicated high-speed-communicationprocessor and between said dedicated high-speed-communication processorand said second processor, wherein each of said data interfacesincludes: a writing-side register group in which data of said processorof a data transmission side is written in response to a clock signal; areading-side register group into which the data written into saidwriting-side register group is transferred and written in response to alater clock operation, the data being read out by a reading-sideprocessor of a data receiving side; write control means for selectivelywriting data in a register in said writing-side register group inaccordance with an address signal and a write signal of the processor ina data-transmitting-side; and read control means for selectively readingdata from a register in said reading-side register group in accordancewith an-address signal of the processor in a data-receiving-side.